Why You Should Build a Superscalar Pipeline Simulator

This abstract describes not only the building of a software simulator of a superscalar pipeline as a teaching tool for Computer Architecture, but also the unanticipated benefits of such a process. My original goal was to build a visual timing simulator of a superscalar pipeline processor for Computer Science students studying pipelines in a junior level Computer Architecture course. However, what I actually built was a steady supply of senior programming projects that combined architecture topics, object-oriented design, and user interface design with several software engineering concepts such as working in teams with fuzzy specifications on a complex project. Secondarily, I saw students benefit by confronting the contrast between the clarity and simplicity of an educational pipeline as found in the Hennessy/Patterson text [1] with the intricate and devious realities of a real processor designed for performance.

BACKGROUND

The Computer Sciences Department at The University of Texas at Austin has a nine-hour undergraduate architecture sequence, culminating in a junior level Computer Architecture course that covers most topics found in [1]. In addition, the architecture course requires a medium-sized programming project to supplement the course. The programming project has historically been an instruction set simulator, with an occasional cache simulation included. My interests are in replacing the instruction set emphasis with advanced concepts of CPU design and an increased focus on non-CPU components of a computer system. I decided to build a visual timing simulator of a superscalar pipeline for the students in order to demonstrate pipeline features that are more modern than those found in a basic five stage fixed point pipeline. My secondary goal for this simulator was to expand the object-oriented programming abilities of the Computer Architecture students by asking them to re-implement a small portion of the superscalar pipeline simulator, given a clean object-oriented design and a well-specified interface to the rest of the simulator.

SIMULATOR DESIGN

The SSVisual601 simulator is a software simulation of both the PowerPC instruction set architecture and the cycle-by-cycle timing of the PowerPC 601 microprocessor. The choice of the processor is a delicate decision. Although, in mid-1995 the PPC604 microprocessor was my first choice, I had to consider that my audience had a limited amount of time to study a new pipeline and would only be familiar with a five stage pipeline. At a minimum, my educational goals were to provide a tool for visualization and self-study on the topics of a fixed point pipeline, a floating point pipeline, out-of-order dispatch, and branch prediction. The PPC601 processor was sufficient without the extra complexities of the PPC604. At this point in 1997 I would resume the search for a processor. The simulation was limited to the processor and cache and omitted simulating exceptions, the MMU, and a realistic interface to physical main memory. The simulator input is an IBM AIX executable file generated by the host RS6000 system.

The object-oriented design is based on the microarchitectural features of the actual PowerPC 601 microprocessor [2] and includes C++ classes for each functional unit and pipeline stage with supporting classes that model instructions, the cache, and memory. The simulator is not event-driven, but instead models a clock cycle with three phases: the start phase at the beginning of the clock cycle for reading state information, the compute phase, and the end phase for writes. Each class contains a method for each of the three phases.

The user interface of the SSVisual601 is a critical component of the project, designed to visually illustrate multiple pipelines, stalls, the prefetching of instructions, branch prediction, and out-of-order dispatch and execution. We chose the Curses library as the user interface tool for building a simple user interface that was easily accessed via modem. The user interface visually displays each instruction as it flows through the pipeline stages. The user interface includes displays of the instruction queue, the fixed point unit, the floating point unit, the branch unit, and the memory hierarchy, with more detailed displays of registers, memory, and the cache for the instruction set architecture component of the simulation.

The simulator was actually built by a total of twelve CS seniors over four semesters of senior projects. The work was handed down from one semester's team to the next. The size of the project and the fuzziness of the PPC 601 data book [2] forced the students to work in teams, to use software engineering design techniques, to write extensive documentation, and to use software control tools. Even the "hackers" on the project were humbled by working on a project that was too large for one person to design or implement.

MY PROPOSAL FOR "YOU"

I am not advocating that you use my PPC601 simulator. Instead, I advocate that you oversee the building of a software simulation of an architectural component, such as a superscalar pipeline processor or a RAID controller. Ostensibly, your audience is a class full of CS architecture students. In reality, you are teaching the seniors who are building this extensive project. I would suggest a maximum of a four semester sequence, since after four semesters, the project can become unwieldy for new students and should only be considered with caution.  I conclude with a broad outline of the four semester sequence:

1. Research/Prototype: students research the design and use of simulators and the choice of microprocessors or other architectural component;
2. Design and build a minimal implementation: students use software engineering techniques to document the design and complete a simplified implementation;
3. Implementation/Test: students critique the design, implement subsets of the the revised design and test; and
4. Implementation/Test/Release: students complete the implementation, test the final product, and produce user documentation.

[1] J. Hennessy, D. Patterson. Computer Architecture: A Quantitative Approach, 2nd ed., Morgan Kaufman, San Francisco, 1996.